1. Field of the Invention
The subject matter of the invention is a susceptor for holding a semiconductor wafer having orientation notch during the deposition of a layer on a front side of the semiconductor wafer. The susceptor has a placement surface for placing the semiconductor wafer in the edge region of a rear side of the semiconductor wafer and a stepped outer delimitation of the placement surface. The subject matter of the invention is also a method for depositing a layer on a semiconductor wafer having orientation notch, in which such a susceptor is used, and a semiconductor wafer made of monocrystalline silicon.
2. Description of the Related Art
Susceptors of the type mentioned are known in various embodiments. An embodiment is described in DE 198 47 101 C1, in which the placement surface is a component of a ring, which forms the susceptor. In the embodiment according to EP 1 460 679 A1, the susceptor additionally has a bottom in the form of a plate. The placement surface is formed by a projection on the plate edge. An embodiment is shown in DE 10 2006 055 038 A1, in which the semiconductor wafer lies in a depression of a ring, and the ring lies on a base plate.
When depositing a layer on the front side of a semiconductor wafer, efforts are made, inter alia, to create a layer having uniform layer thickness and to have the usable surface of the layer extend as close as possible to the edge of the semiconductor wafer. When attempting to implement this specification, one is confronted with the problem that flatness problems occur in the region of an orientation notch of the semiconductor wafer, the causes of which are a greater layer thickness and material deposits on the rear side of the semiconductor wafer. To remedy this problem, it is proposed in US 2012/0270407 A1 and JP 2013-51290 that the placement surface of the susceptor be enlarged inward at one point and the semiconductor wafer be laid on the susceptor such that the orientation notch comes to rest on the placement surface at this point.
US 2013/0264690 A1 relates to the improvement of the flatness of a semiconductor wafer having an epitaxial layer, in particular in the edge region of the semiconductor wafer. The local geometry in the edge region of the front side, expressed by ESFQRmean and in consideration of an edge exclusion of 1 mm, is not greater than 100 nm.
Notwithstanding the cited prior art, the demand still exists for improving the local flatness of a coated semiconductor wafer in the region of the orientation notch.